10.4. Running a Design on Nexys Video
10.4.1. Nexys Video Instructions
The default Digilent Nexys Video harness uses a TSI-over-UART adapter to bringup the FPGA.
A user can connect to the Nexys Video target using a special uart_tsi program that opens a UART TTY.
The interface for the uart_tsi program provides unique functionality that is useful for bringing up test chips.
An example tweaks + Rocket config fragment can be found below:
// https://ucb.bar/chipyard/fpga/src/main/scala/nexysvideo/Configs.scala
class WithNexysVideoTweaks(freqMHz: Double = 50) extends Config(
new WithNexysVideoUARTTSI ++
new WithNexysVideoDDRTL ++
new WithNoDesignKey ++
new testchipip.tsi.WithUARTTSIClient ++
new chipyard.harness.WithSerialTLTiedOff ++
new chipyard.harness.WithHarnessBinderClockFreqMHz(freqMHz) ++
new chipyard.config.WithUniformBusFrequencies(freqMHz) ++
new chipyard.harness.WithAllClocksFromHarnessClockInstantiator ++
new chipyard.clocking.WithPassthroughClockGenerator ++
new chipyard.config.WithNoDebug ++ // no jtag
new chipyard.config.WithNoUART ++ // use UART for the UART-TSI thing instad
new chipyard.config.WithTLBackingMemory ++ // FPGA-shells converts the AXI to TL for us
new freechips.rocketchip.subsystem.WithExtMemSize(BigInt(512) << 20) ++ // 512mb on Nexys Video
new freechips.rocketchip.subsystem.WithoutTLMonitors)
class RocketNexysVideoConfig extends Config(
new WithNexysVideoTweaks ++
new chipyard.config.WithBroadcastManager ++ // no l2
new chipyard.RocketConfig)
To build the design (Vivado should be added to the PATH), run:
cd fpga/
make SUB_PROJECT=nexysvideo bitstream
To build the UART-based frontend server, run:
cd generators/testchipip/uart_tsi
make
After programming the bitstream, and connecting the Nexys Video’s UART to a host PC via the USB cable, the uart_tsi program can be run to interact with the target.
Running a program:
./uart_tsi +tty=/dev/ttyUSBX dhrystone.riscv
Probe an address on the target system:
./uart_tsi +tty=/dev/ttyUSBX +init_read=0x10000 none
Write some address before running a program:
./uart_tsi +tty=/dev/ttyUSBX +init_write=0x80000000:0xdeadbeef none
Self-check that binary loading proceeded correctly:
./uart_tsi +tty=/dev/ttyUSBX +selfcheck dhrystone.riscv