VexiiRiscv Core
===================================
`VexiiRiscv <https://github.com/SpinalHDL/VexiiRiscv>`__ is a RV64IMAFDCB in-order superscalar core implemented in `SpinalHDL <https://spinalhdl.github.io/SpinalDoc-RTD/master/index.html#>`__.
VexiiRiscv is Linux-capable and achieves competitive IPC in its design class.
VexiiRiscv implements cache-coherent TileLink L1 data caches and is integrated as a selectable Tile in Chipyard.

The example VexiiRiscv config is ``VexiiRiscvConfig``.
When building this Config, Chipyard will call VexiiRiscv's SpinalHDL RTL generator to generate the core's SystemVerilog, before `wrapping <https://github.com/ucb-bar/vexiiriscv-tile>`__ it as a Chisel blackbox.

Configuration classes and Chipyard glue for VexiiRiscv live under ``generators/vexiiriscv/chipyard`` and are compiled directly from the VexiiRiscv repository sources. After running the standard setup (``./build-setup.sh``), build the example config with:

::

  cd sims/vcs && make CONFIG=VexiiRiscvConfig