1.2.0
  • 1. Chipyard Basics
    • 1.1. Chipyard Components
      • 1.1.1. Generators
        • 1.1.1.1. Processor Cores
        • 1.1.1.2. Accelerators
        • 1.1.1.3. System Components:
      • 1.1.2. Tools
      • 1.1.3. Toolchains
      • 1.1.4. Software
      • 1.1.5. Sims
      • 1.1.6. VLSI
    • 1.2. Development Ecosystem
      • 1.2.1. Chipyard Approach
      • 1.2.2. Chisel/FIRRTL
      • 1.2.3. RTL Generators
    • 1.3. Configs, Parameters, Mixins, and Everything In Between
      • 1.3.1. Parameters
      • 1.3.2. Configs
      • 1.3.3. Cake Pattern / Mixin
      • 1.3.4. Additional References
    • 1.4. Initial Repository Setup
      • 1.4.1. Requirements
      • 1.4.2. Checking out the sources
      • 1.4.3. Building a Toolchain
  • 2. Simulation
    • 2.1. Software RTL Simulation
      • 2.1.1. Verilator (Open-Source)
      • 2.1.2. Synopsys VCS (License Required)
      • 2.1.3. Choice of Simulator
      • 2.1.4. Simulating The Default Example
      • 2.1.5. Simulating A Custom Project
      • 2.1.6. Generating Waveforms
    • 2.2. FPGA-Accelerated Simulation
      • 2.2.1. FireSim
      • 2.2.2. Running your Design in FireSim
  • 3. Included RTL Generators
    • 3.1. Rocket Chip
      • 3.1.1. Tiles
      • 3.1.2. Memory System
      • 3.1.3. MMIO
      • 3.1.4. DMA
    • 3.2. Rocket Core
    • 3.3. Berkeley Out-of-Order Machine (BOOM)
    • 3.4. Hwacha
    • 3.5. Gemmini
      • 3.5.1. Generator Parameters
      • 3.5.2. Gemmini Software
        • 3.5.2.1. Build and Run Gemmini Tests
      • 3.5.3. Alternative SoC Configs
    • 3.6. IceNet
      • 3.6.1. Controller
      • 3.6.2. Send Path
      • 3.6.3. Receive Path
      • 3.6.4. Pause Handler
      • 3.6.5. Linux Driver
      • 3.6.6. Configuration
    • 3.7. Test Chip IP
      • 3.7.1. Serial Adapter
      • 3.7.2. Block Device Controller
      • 3.7.3. TileLink SERDES
      • 3.7.4. TileLink Switcher
      • 3.7.5. UART Adapter
    • 3.8. SiFive Generators
      • 3.8.1. Last-Level Cache Generator
      • 3.8.2. Peripheral Devices
    • 3.9. SHA3 RoCC Accelerator
      • 3.9.1. Introduction
      • 3.9.2. Technical Details
      • 3.9.3. Using a SHA3 Accelerator
    • 3.10. Ariane Core
  • 4. Development Tools
    • 4.1. Chisel
    • 4.2. FIRRTL
    • 4.3. Treadle and FIRRTL Interpreter
    • 4.4. Chisel Testers
    • 4.5. Dsptools
    • 4.6. Barstools
      • 4.6.1. Mapping technology SRAMs (MacroCompiler)
        • 4.6.1.1. MacroCompiler Options
        • 4.6.1.2. SRAM MDF Fields
      • 4.6.2. Separating the Top module from the TestHarness module
      • 4.6.3. Macro Description Format
      • 4.6.4. Mapping technology IO cells
  • 5. VLSI Flow
    • 5.1. Building A Chip
      • 5.1.1. Transforming the RTL
        • 5.1.1.1. Modifying the logical hierarchy
      • 5.1.2. Creating a floorplan
      • 5.1.3. Running the VLSI flow
    • 5.2. Core Hammer
      • 5.2.1. Actions
      • 5.2.2. Steps
      • 5.2.3. Hooks
    • 5.3. Configuration (Hammer IR)
    • 5.4. Tool Plugins
    • 5.5. Technology Plugins
    • 5.6. ASAP7 Tutorial
      • 5.6.1. Project Structure
      • 5.6.2. Prerequisites
      • 5.6.3. Initial Setup
      • 5.6.4. Building the Design
      • 5.6.5. Running the VLSI Flow
        • 5.6.5.1. example-vlsi
        • 5.6.5.2. example.yml
        • 5.6.5.3. Synthesis
        • 5.6.5.4. Place-and-Route
        • 5.6.5.5. DRC & LVS
    • 5.7. Advanced Usage
      • 5.7.1. Alternative RTL Flows
      • 5.7.2. Under the Hood
      • 5.7.3. Manual Step Execution & Dependency Tracking
      • 5.7.4. RTL and Gate-level Simulation
  • 6. Customization
    • 6.1. Heterogeneous SoCs
      • 6.1.1. Creating a Rocket and BOOM System
      • 6.1.2. Adding Hwachas
      • 6.1.3. Assigning Accelerators to Specific Tiles with MultiRoCC
    • 6.2. Integrating Custom Chisel Projects into the Generator Build System
    • 6.3. RoCC vs MMIO
    • 6.4. Adding a RoCC Accelerator
      • 6.4.1. Adding RoCC accelerator to Config
    • 6.5. MMIO Peripherals
      • 6.5.1. Advanced Features of RegField Entries
      • 6.5.2. Connecting by TileLink
      • 6.5.3. Top-level Traits
      • 6.5.4. Constructing the Top and Config
      • 6.5.5. Testing
    • 6.6. Keys, Traits, and Configs
      • 6.6.1. Keys
      • 6.6.2. Traits
      • 6.6.3. Config Fragments
    • 6.7. Adding a DMA Device
    • 6.8. Incorporating Verilog Blocks
      • 6.8.1. Adding a Verilog Blackbox Resource File
      • 6.8.2. Defining a Chisel BlackBox
      • 6.8.3. Instantiating the BlackBox and Defining MMIO
      • 6.8.4. Defining a Chip with a BlackBox
      • 6.8.5. Software Testing
      • 6.8.6. Support for Verilog Within Chipyard Tool Flows
    • 6.9. Memory Hierarchy
      • 6.9.1. The L1 Caches
      • 6.9.2. The SiFive L2 Cache
      • 6.9.3. The Broadcast Hub
      • 6.9.4. The Outer Memory System
    • 6.10. Chipyard Boot Process
      • 6.10.1. BootROM and RISC-V Frontend Server
      • 6.10.2. The Berkeley Boot Loader and RISC-V Linux
    • 6.11. Adding a Firrtl Transform
      • 6.11.1. Where to add transforms
      • 6.11.2. Examples of transforms
    • 6.12. IOBinders
  • 7. Target Software
    • 7.1. FireMarshal
    • 7.2. The RISC-V ISA Simulator (Spike)
  • 8. Advanced Concepts
    • 8.1. Tops, Test-Harnesses, and the Test-Driver
      • 8.1.1. Top/DUT
        • 8.1.1.1. BaseSubsystem
        • 8.1.1.2. Subsystem
        • 8.1.1.3. System
        • 8.1.1.4. Tops
      • 8.1.2. TestHarness
      • 8.1.3. TestDriver
    • 8.2. Communicating with the DUT
      • 8.2.1. Using the Tethered Serial Interface (TSI) or the Debug Module Interface (DMI)
        • 8.2.1.1. Primer on the Front-End Server (FESVR)
        • 8.2.1.2. Using the Tethered Serial Interface (TSI)
        • 8.2.1.3. Using the Debug Module Interface (DMI)
        • 8.2.1.4. Starting the TSI or DMI Simulation
      • 8.2.2. Using the JTAG Interface
        • 8.2.2.1. Creating a DTM+JTAG Config
        • 8.2.2.2. Building a DTM+JTAG Simulator
        • 8.2.2.3. Debugging with JTAG
    • 8.3. Debugging RTL
      • 8.3.1. Waveforms
      • 8.3.2. Print Output
      • 8.3.3. Basic tests
      • 8.3.4. Torture tests
      • 8.3.5. Firesim Debugging
    • 8.4. Accessing Scala Resources
    • 8.5. Context-Dependent-Environments
      • 8.5.1. Site
      • 8.5.2. Here
      • 8.5.3. Up
  • 9. TileLink and Diplomacy Reference
    • 9.1. TileLink Node Types
      • 9.1.1. Client Node
      • 9.1.2. Manager Node
      • 9.1.3. Register Node
      • 9.1.4. Identity Node
      • 9.1.5. Adapter Node
      • 9.1.6. Nexus Node
    • 9.2. Diplomacy Connectors
      • 9.2.1. :=
      • 9.2.2. :=*
      • 9.2.3. :*=
      • 9.2.4. :*=*
    • 9.3. TileLink Edge Object Methods
      • 9.3.1. Get
      • 9.3.2. Put
      • 9.3.3. Arithmetic
      • 9.3.4. Logical
      • 9.3.5. Hint
      • 9.3.6. AccessAck
      • 9.3.7. HintAck
      • 9.3.8. first
      • 9.3.9. last
      • 9.3.10. done
      • 9.3.11. count
      • 9.3.12. numBeats
      • 9.3.13. numBeats1
      • 9.3.14. hasData
    • 9.4. Register Router
      • 9.4.1. Basic Usage
      • 9.4.2. Decoupled Interfaces
      • 9.4.3. Using Functions
      • 9.4.4. Register Routers for Other Protocols
    • 9.5. Diplomatic Widgets
      • 9.5.1. TLBuffer
      • 9.5.2. AXI4Buffer
      • 9.5.3. AXI4UserYanker
      • 9.5.4. AXI4Deinterleaver
      • 9.5.5. TLFragmenter
      • 9.5.6. AXI4Fragmenter
      • 9.5.7. TLSourceShrinker
      • 9.5.8. AXI4IdIndexer
      • 9.5.9. TLWidthWidget
      • 9.5.10. TLFIFOFixer
      • 9.5.11. TLXbar and AXI4Xbar
      • 9.5.12. TLToAXI4 and AXI4ToTL
      • 9.5.13. TLROM
      • 9.5.14. TLRAM and AXI4RAM
Chipyard
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  • 5. VLSI Flow
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5. VLSI FlowΒΆ

The Chipyard framework aims to provide wrappers for a general VLSI flow. In particular, we aim to support the Hammer physical design generator flow.

VLSI Flow:

  • 5.1. Building A Chip
    • 5.1.1. Transforming the RTL
    • 5.1.2. Creating a floorplan
    • 5.1.3. Running the VLSI flow
  • 5.2. Core Hammer
    • 5.2.1. Actions
    • 5.2.2. Steps
    • 5.2.3. Hooks
  • 5.3. Configuration (Hammer IR)
  • 5.4. Tool Plugins
  • 5.5. Technology Plugins
  • 5.6. ASAP7 Tutorial
    • 5.6.1. Project Structure
    • 5.6.2. Prerequisites
    • 5.6.3. Initial Setup
    • 5.6.4. Building the Design
    • 5.6.5. Running the VLSI Flow
  • 5.7. Advanced Usage
    • 5.7.1. Alternative RTL Flows
    • 5.7.2. Under the Hood
    • 5.7.3. Manual Step Execution & Dependency Tracking
    • 5.7.4. RTL and Gate-level Simulation
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