5.8. Sky130 Tutorial
The vlsi
folder of this repository contains an example Hammer flow with the TinyRocketConfig from Chipyard. This example tutorial uses the built-in Sky130 technology plugin and requires access to the included Cadence and Mentor tool plugin submodules. Cadence is necessary for synthesis & place-and-route, while Mentor is needed for DRC & LVS.
5.8.1. Project Structure
This example gives a suggested file structure and build system. The vlsi/
folder will eventually contain the following files and folders:
Makefile
,sim.mk
,power.mk
Integration of Hammer’s build system into Chipyard and abstracts away some Hammer commands.
build
Hammer output directory. Can be changed with the
OBJ_DIR
variable.Will contain subdirectories such as
syn-rundir
andpar-rundir
and theinputs.yml
denoting the top module and input Verilog files.
env.yml
A template file for tool environment configuration. Fill in the install and license server paths for your environment.
example-vlsi-sky130
Entry point to Hammer. Contains example placeholders for hooks.
example-sky130.yml
,example-tools.yml
,example-designs/sky130-commercial.yml
Hammer IR for this tutorial.
example-design.yml
,example-asap7.yml
,example-tech.yml
Hammer IR not used for this tutorial but provided as templates.
generated-src
All of the elaborated Chisel and FIRRTL.
hammer
,hammer-<vendor>-plugins
,hammer-<tech>-plugin
Core, tool, tech repositories.
5.8.2. Prerequisites
Python 3.6+
numpy package
Genus, Innovus, Voltus, VCS, and Calibre licenses
Sky130 PDK, install using these directions
5.8.3. Initial Setup
In the Chipyard root, run:
./scripts/init-vlsi.sh sky130
to pull the Hammer & plugin submodules. Note that for technologies other than sky130
or asap7
, the tech submodule must be added in the vlsi
folder first.
Pull the Hammer environment into the shell:
cd vlsi
export HAMMER_HOME=$PWD/hammer
source $HAMMER_HOME/sourceme.sh
5.8.4. Building the Design
To elaborate the TinyRocketConfig
and set up all prerequisites for the build system to push the design and SRAM macros through the flow:
make buildfile tutorial=sky130-commercial
The command make buildfile
generates a set of Make targets in build/hammer.d
.
It needs to be re-run if environment variables are changed.
It is recommended that you edit these variables directly in the Makefile rather than exporting them to your shell environment.
For the purpose of brevity, in this tutorial we will set the Make variable tutorial=sky130-commercial
,
which will cause additional variables to be set in tutorial.mk
, a few of which are summarized as follows:
CONFIG=TinyRocketConfig
selects the target generator config in the same manner as the rest of the Chipyard framework. This elaborates a stripped-down Rocket Chip in the interest of minimizing tool runtime.tech_name=sky130
sets a few more necessary paths in theMakefile
, such as the appropriate Hammer pluginTOOLS_CONF
andTECH_CONF
select the approproate YAML configuration files,example-tools.yml
andexample-sky130.yml
, which are described belowDESIGN_CONF
andEXTRA_CONFS
allow for additonal design-specific overrides of the Hammer IR inexample-sky130.yml
VLSI_OBJ_DIR=build-sky130-commercial
gives the build directory a unique name to allow running multiple flows in the same repo. Note that for the rest of the tutorial we will still refer to this directory in file paths asbuild
, again for brevity.VLSI_TOP
is by defaultChipTop
, which is the name of the top-level Verilog module generated in the Chipyard SoC configs. By instead settingVLSI_TOP=Rocket
, we can use the Rocket core as the top-level module for the VLSI flow, which consists only of a single RISC-V core (and no caches, peripherals, buses, etc). This is useful to run through this tutorial quickly, and does not rely on any SRAMs.
5.8.5. Running the VLSI Flow
5.8.5.1. example-vlsi-sky130
This is the entry script with placeholders for hooks. In the ExampleDriver
class, a list of hooks is passed in the get_extra_par_hooks
. Hooks are additional snippets of python and TCL (via x.append()
) to extend the Hammer APIs. Hooks can be inserted using the make_pre/post/replacement_hook
methods as shown in this example. Refer to the Hammer documentation on hooks for a detailed description of how these are injected into the VLSI flow.
5.8.5.2. example-sky130.yml
This contains the Hammer configuration for this example project. Example clock constraints, power straps definitions, placement constraints, and pin constraints are given. Additional configuration for the extra libraries and tools are at the bottom.
First, set technology.sky130.sky130A/sky130_nda/openram_lib
to the absolute path of the respective directories containing the Sky130 PDK and SRAM files. See the
Sky130 Hammer plugin README
for details about the PDK setup.
5.8.5.3. example-tools.yml
This contains the Hammer configuration for a commercial tool flow. It selects tools for synthesis (Cadence Genus), place and route (Cadence Innovus), DRC and LVS (Mentor Calibre).
5.8.5.4. Synthesis
make syn tutorial=sky130-commercial
Post-synthesis logs and collateral are in build/syn-rundir
. The raw quality of results data is available at build/syn-rundir/reports
, and methods to extract this information for design space exploration are a work in progress.
5.8.5.5. Place-and-Route
make par tutorial=sky130-commercial
After completion, the final database can be opened in an interactive Innovus session via ./build/par-rundir/generated-scripts/open_chip
.
Intermediate database are written in build/par-rundir
between each step of the par
action, and can be restored in an interactive Innovus session as desired for debugging purposes.
Timing reports are found in build/par-rundir/timingReports
. They are gzipped text files.
5.8.5.6. DRC & LVS
To run DRC & LVS, and view the results in Calibre:
make drc tutorial=sky130-commercial
./build/chipyard.TestHarness.TinyRocketConfig-ChipTop/drc-rundir/generated-scripts/view_drc
make lvs tutorial=sky130-commercial
./build/chipyard.TestHarness.TinyRocketConfig-ChipTop/lvs-rundir/generated-scripts/view_lvs
Some DRC errors are expected from this PDK, especially with regards to the SRAMs, as explained in the
Sky130 Hammer plugin README.
For this reason, the example-vlsi-sky130
script black-boxes the SRAMs for DRC/LVS analysis.
5.8.5.7. Simulation
Simulation with VCS is supported, and can be run at the RTL- or gate-level (post-synthesis and post-P&R). The simulation infrastructure as included here is intended for running RISC-V binaries on a Chipyard config. For example, for an RTL-level simulation:
make sim-rtl tutorial=sky130-commercial BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/isa/rv64ui-p-simple
Post-synthesis and post-P&R simulations use the sim-syn
and sim-par
make targets, respectively.
Appending -debug
and -debug-timing
to these make targets will instruct VCS to write a SAIF + VPD (or FSDB if the USE_FSDB
flag is set) and do timing-annotated simulations, respectively. See the sim.mk
file for all available targets.
5.8.5.8. Power/Rail Analysis
Post-P&R power and rail (IR drop) analysis is supported with Voltus:
make power-par tutorial=sky130-commercial
If you append the BINARY
variable to the command, it will use the activity file generated from a sim-<syn/par>-debug
run and report dynamic power & IR drop from the toggles encoded in the waveform.
To bypass gate-level simulation, you will need to run the power tool manually (see the generated commands in the generated hammer.d
buildfile). Static and active (vectorless) power & IR drop will be reported.