Logo
run-ci
  • 1. Chipyard Basics
    • 1.1. Chipyard Components
      • 1.1.1. Generators
        • 1.1.1.1. Processor Cores
        • 1.1.1.2. Accelerators
        • 1.1.1.3. System Components:
      • 1.1.2. Tools
      • 1.1.3. Toolchains
      • 1.1.4. Software
      • 1.1.5. Sims
      • 1.1.6. Prototyping
      • 1.1.7. VLSI
    • 1.2. Development Ecosystem
      • 1.2.1. Chipyard Approach
      • 1.2.2. Chisel/FIRRTL
      • 1.2.3. RTL Generators
    • 1.3. Configs, Parameters, Mixins, and Everything In Between
      • 1.3.1. Parameters
      • 1.3.2. Configs
      • 1.3.3. Cake Pattern / Mixin
      • 1.3.4. Additional References
    • 1.4. Initial Repository Setup
      • 1.4.1. Prerequisites
        • 1.4.1.1. Running on AWS EC2 with FireSim
        • 1.4.1.2. Default Requirements Installation
      • 1.4.2. Setting up the Chipyard Repo
      • 1.4.3. Sourcing env.sh
      • 1.4.4. Pre-built Docker Image
      • 1.4.5. What’s Next?
      • 1.4.6. Upgrading Chipyard Release Versions
  • 2. Simulation
    • 2.1. Software RTL Simulation
      • 2.1.1. Verilator (Open-Source)
      • 2.1.2. Synopsys VCS (License Required)
      • 2.1.3. Choice of Simulator
      • 2.1.4. Simulating The Default Example
      • 2.1.5. Makefile Variables and Commands
      • 2.1.6. Simulating A Custom Project
      • 2.1.7. Fast Memory Loading
      • 2.1.8. Generating Waveforms
      • 2.1.9. Additional Verilator Options
    • 2.2. FPGA-Accelerated Simulation
      • 2.2.1. FireSim
      • 2.2.2. Running your Design in FireSim
  • 3. Included RTL Generators
    • 3.1. Rocket Chip
      • 3.1.1. Tiles
      • 3.1.2. Memory System
      • 3.1.3. MMIO
      • 3.1.4. DMA
    • 3.2. Rocket Core
    • 3.3. Berkeley Out-of-Order Machine (BOOM)
    • 3.4. Constellation
    • 3.5. Hwacha
    • 3.6. Gemmini
    • 3.7. IceNet
      • 3.7.1. Controller
      • 3.7.2. Send Path
      • 3.7.3. Receive Path
      • 3.7.4. Pause Handler
      • 3.7.5. Linux Driver
      • 3.7.6. Configuration
    • 3.8. Test Chip IP
      • 3.8.1. Serial Adapter
      • 3.8.2. Block Device Controller
      • 3.8.3. TileLink SERDES
      • 3.8.4. TileLink Switcher
      • 3.8.5. TileLink Ring Network
      • 3.8.6. UART Adapter
      • 3.8.7. SPI Flash Model
    • 3.9. SiFive Generators
      • 3.9.1. Last-Level Cache Generator
      • 3.9.2. Peripheral Devices
    • 3.10. SHA3 RoCC Accelerator
      • 3.10.1. Introduction
      • 3.10.2. Technical Details
      • 3.10.3. Using a SHA3 Accelerator
    • 3.11. CVA6 Core
    • 3.12. Ibex Core
    • 3.13. FFT Generator
      • 3.13.1. Configuration
      • 3.13.2. Usage and Testing
      • 3.13.3. Acknowledgements
    • 3.14. NVDLA
      • 3.14.1. NVDLA Software with FireMarshal
    • 3.15. Sodor Core
    • 3.16. Mempress
  • 4. Development Tools
    • 4.1. Chisel
    • 4.2. FIRRTL
    • 4.3. Treadle and FIRRTL Interpreter
    • 4.4. Chisel Testers
    • 4.5. Dsptools
    • 4.6. Barstools
      • 4.6.1. Mapping technology SRAMs (MacroCompiler)
        • 4.6.1.1. MacroCompiler Options
        • 4.6.1.2. SRAM MDF Fields
      • 4.6.2. Separating the Top module from the TestHarness module
      • 4.6.3. Macro Description Format
      • 4.6.4. Mapping technology IO cells
    • 4.7. Dromajo
  • 5. VLSI Flow
    • 5.1. Building A Chip
      • 5.1.1. Transforming the RTL
        • 5.1.1.1. Modifying the logical hierarchy
      • 5.1.2. Creating a floorplan
      • 5.1.3. Running the VLSI tool flow
    • 5.2. Core Hammer
      • 5.2.1. Actions
      • 5.2.2. Steps
      • 5.2.3. Hooks
      • 5.2.4. VLSI Flow Control
    • 5.3. Configuration (Hammer IR)
    • 5.4. Tool Plugins
    • 5.5. Technology Plugins
    • 5.6. Using Hammer To Place and Route a Custom Block
      • 5.6.1. Initialize the Hammer Plug-ins
      • 5.6.2. Setting up the Hammer Configuration Files
      • 5.6.3. Building the Design
      • 5.6.4. Running the VLSI Flow
        • 5.6.4.1. Synthesis
        • 5.6.4.2. Place-and-Route
        • 5.6.4.3. Power Estimation
        • 5.6.4.4. Signoff
      • 5.6.5. Customizing Your VLSI Flow in Hammer
        • 5.6.5.1. Advanced Environment Setup
        • 5.6.5.2. Composing a Hierarchical Design
        • 5.6.5.3. Customizing Generated Tcl Scripts
    • 5.7. ASAP7 Tutorial
      • 5.7.1. Project Structure
      • 5.7.2. Prerequisites
      • 5.7.3. Initial Setup
      • 5.7.4. Building the Design
      • 5.7.5. Running the VLSI Flow
        • 5.7.5.1. example-vlsi
        • 5.7.5.2. example-asap7.yml
        • 5.7.5.3. Synthesis
        • 5.7.5.4. Place-and-Route
        • 5.7.5.5. DRC & LVS
        • 5.7.5.6. Simulation
        • 5.7.5.7. Power/Rail Analysis
    • 5.8. Sky130 Tutorial
      • 5.8.1. Project Structure
      • 5.8.2. Prerequisites
      • 5.8.3. Initial Setup
      • 5.8.4. Building the Design
      • 5.8.5. Running the VLSI Flow
        • 5.8.5.1. example-vlsi-sky130
        • 5.8.5.2. example-sky130.yml
        • 5.8.5.3. example-tools.yml
        • 5.8.5.4. Synthesis
        • 5.8.5.5. Place-and-Route
        • 5.8.5.6. DRC & LVS
        • 5.8.5.7. Simulation
        • 5.8.5.8. Power/Rail Analysis
    • 5.9. Sky130 + OpenROAD Tutorial
      • 5.9.1. Project Structure
      • 5.9.2. Prerequisites
      • 5.9.3. Initial Setup
      • 5.9.4. Building the Design
      • 5.9.5. Running the VLSI Flow
        • 5.9.5.1. example-vlsi-sky130
        • 5.9.5.2. example-sky130.yml
        • 5.9.5.3. example-openroad.yml
        • 5.9.5.4. Synthesis
        • 5.9.5.5. Place-and-Route
        • 5.9.5.6. DRC & LVS
        • 5.9.5.7. VLSI Flow Control
      • 5.9.6. Documentation
    • 5.10. Advanced Usage
      • 5.10.1. Alternative RTL Flows
      • 5.10.2. Under the Hood
      • 5.10.3. Manual Step Execution & Dependency Tracking
      • 5.10.4. Hierarchical RTL/Gate-level Simulation, Power Estimation
  • 6. Customization
    • 6.1. Heterogeneous SoCs
      • 6.1.1. Creating a Rocket and BOOM System
      • 6.1.2. Adding Hwachas
      • 6.1.3. Assigning Accelerators to Specific Tiles with MultiRoCC
    • 6.2. SoCs with NoC-based Interconnects
      • 6.2.1. Private Interconnects
      • 6.2.2. Shared Global Interconnect
    • 6.3. Integrating Custom Chisel Projects into the Generator Build System
    • 6.4. Adding a custom core
      • 6.4.1. Wrap Verilog Module with Blackbox (Optional)
      • 6.4.2. Create Parameter Case Classes
      • 6.4.3. Create Tile Class
      • 6.4.4. Connect TileLink Buses
      • 6.4.5. Create Implementation Class
      • 6.4.6. Connect Interrupt
      • 6.4.7. Create Config Fragments to Integrate the Core
    • 6.5. RoCC vs MMIO
    • 6.6. Adding a RoCC Accelerator
      • 6.6.1. Adding RoCC accelerator to Config
    • 6.7. MMIO Peripherals
      • 6.7.1. Advanced Features of RegField Entries
      • 6.7.2. Connecting by TileLink
      • 6.7.3. Top-level Traits
      • 6.7.4. Constructing the DigitalTop and Config
      • 6.7.5. Testing
    • 6.8. Dsptools Blocks
      • 6.8.1. Creating a DspBlock
      • 6.8.2. Connecting DspBlock by TileLink
      • 6.8.3. Top Level Traits
      • 6.8.4. Constructing the Top and Config
      • 6.8.5. FIR Testing
    • 6.9. Keys, Traits, and Configs
      • 6.9.1. Keys
      • 6.9.2. Traits
      • 6.9.3. Config Fragments
    • 6.10. Adding a DMA Device
    • 6.11. Incorporating Verilog Blocks
      • 6.11.1. Adding a Verilog Blackbox Resource File
      • 6.11.2. Defining a Chisel BlackBox
      • 6.11.3. Instantiating the BlackBox and Defining MMIO
      • 6.11.4. Defining a Chip with a BlackBox
      • 6.11.5. Software Testing
      • 6.11.6. Support for Verilog Within Chipyard Tool Flows
    • 6.12. Memory Hierarchy
      • 6.12.1. The L1 Caches
      • 6.12.2. The System Bus
      • 6.12.3. The SiFive L2 Cache
      • 6.12.4. The Broadcast Hub
      • 6.12.5. The Outer Memory System
    • 6.13. Chipyard Boot Process
      • 6.13.1. BootROM and RISC-V Frontend Server
      • 6.13.2. The Berkeley Boot Loader and RISC-V Linux
    • 6.14. Adding a Firrtl Transform
      • 6.14.1. Where to add transforms
      • 6.14.2. Examples of transforms
    • 6.15. IOBinders and HarnessBinders
      • 6.15.1. IOBinders
      • 6.15.2. HarnessBinders
  • 7. Target Software
    • 7.1. FireMarshal
    • 7.2. The RISC-V ISA Simulator (Spike)
    • 7.3. Baremetal RISC-V Programs
  • 8. Advanced Concepts
    • 8.1. Tops, Test-Harnesses, and the Test-Driver
      • 8.1.1. ChipTop/DUT
      • 8.1.2. System/DigitalTop
        • 8.1.2.1. BaseSubsystem
        • 8.1.2.2. Subsystem
        • 8.1.2.3. System
        • 8.1.2.4. Tops
      • 8.1.3. TestHarness
      • 8.1.4. TestDriver
    • 8.2. Communicating with the DUT
      • 8.2.1. Using the Tethered Serial Interface (TSI) or the Debug Module Interface (DMI)
        • 8.2.1.1. Primer on the Front-End Server (FESVR)
        • 8.2.1.2. Using the Tethered Serial Interface (TSI)
        • 8.2.1.3. Using the Debug Module Interface (DMI)
        • 8.2.1.4. Starting the TSI or DMI Simulation
      • 8.2.2. Using the JTAG Interface
        • 8.2.2.1. Debugging with JTAG
      • 8.2.3. Example Test Chip Bringup Communication
        • 8.2.3.1. Intro to Typical Chipyard Test Chip
        • 8.2.3.2. Simulation Setup of the Example Test Chip
        • 8.2.3.3. Bringup Setup of the Example Test Chip after Tapeout
    • 8.3. Debugging RTL
      • 8.3.1. Waveforms
      • 8.3.2. Print Output
      • 8.3.3. Basic tests
      • 8.3.4. Torture tests
      • 8.3.5. Firesim Debugging
    • 8.4. Debugging BOOM
      • 8.4.1. Setting up Dromajo Co-simulation
    • 8.5. Accessing Scala Resources
    • 8.6. Context-Dependent-Environments
      • 8.6.1. Site
      • 8.6.2. Here
      • 8.6.3. Up
    • 8.7. Creating Clocks in the Test Harness
    • 8.8. Managing Published Scala Dependencies
      • 8.8.1. Publishing Local Changes
  • 9. TileLink and Diplomacy Reference
    • 9.1. TileLink Node Types
      • 9.1.1. Client Node
      • 9.1.2. Manager Node
      • 9.1.3. Register Node
      • 9.1.4. Identity Node
      • 9.1.5. Adapter Node
      • 9.1.6. Nexus Node
    • 9.2. Diplomacy Connectors
      • 9.2.1. :=
      • 9.2.2. :=*
      • 9.2.3. :*=
      • 9.2.4. :*=*
    • 9.3. TileLink Edge Object Methods
      • 9.3.1. Get
      • 9.3.2. Put
      • 9.3.3. Arithmetic
      • 9.3.4. Logical
      • 9.3.5. Hint
      • 9.3.6. AccessAck
      • 9.3.7. HintAck
      • 9.3.8. first
      • 9.3.9. last
      • 9.3.10. done
      • 9.3.11. count
      • 9.3.12. numBeats
      • 9.3.13. numBeats1
      • 9.3.14. hasData
    • 9.4. Register Router
      • 9.4.1. Basic Usage
      • 9.4.2. Decoupled Interfaces
      • 9.4.3. Using Functions
      • 9.4.4. Register Routers for Other Protocols
    • 9.5. Diplomatic Widgets
      • 9.5.1. TLBuffer
      • 9.5.2. AXI4Buffer
      • 9.5.3. AXI4UserYanker
      • 9.5.4. AXI4Deinterleaver
      • 9.5.5. TLFragmenter
      • 9.5.6. AXI4Fragmenter
      • 9.5.7. TLSourceShrinker
      • 9.5.8. AXI4IdIndexer
      • 9.5.9. TLWidthWidget
      • 9.5.10. TLFIFOFixer
      • 9.5.11. TLXbar and AXI4Xbar
      • 9.5.12. TLToAXI4 and AXI4ToTL
      • 9.5.13. TLROM
      • 9.5.14. TLRAM and AXI4RAM
  • 10. Prototyping Flow
    • 10.1. General Setup and Usage
      • 10.1.1. Sources and Submodule Setup
      • 10.1.2. Generating a Bitstream
      • 10.1.3. Debugging with ILAs on Supported FPGAs
    • 10.2. Running a Design on VCU118
      • 10.2.1. Basic VCU118 Design
      • 10.2.2. Brief Implementation Description + More Complicated Designs
      • 10.2.3. Introduction to the Bringup Design
      • 10.2.4. Running Linux on VCU118 Designs
        • 10.2.4.1. Building Linux with FireMarshal
        • 10.2.4.2. Setting up the SDCard
        • 10.2.4.3. Transfer and Run Linux from the SDCard
    • 10.3. Running a Design on Arty
      • 10.3.1. Basic Arty Design
      • 10.3.2. Brief Implementation Description and Guidance for Adding/Changing Xilinx Collateral
Chipyard
  • »
  • 9. TileLink and Diplomacy Reference »
  • 9.1. TileLink Node Types
  • Edit on GitHub

9.1. TileLink Node Types

Diplomacy represents the different components of an SoC as nodes of a directed acyclic graph. TileLink nodes can come in several different types.

9.1.1. Client Node

TileLink clients are modules that initiate TileLink transactions by sending requests on the A channel and receive responses on the D channel. If the client implements TL-C, it will receive probes on the B channel, send releases on the C channel, and send grant acknowledgements on the E channel.

The L1 caches and DMA devices in RocketChip/Chipyard have client nodes.

You can add a TileLink client node to your LazyModule using the TLHelper object from testchipip like so:

class MyClient(implicit p: Parameters) extends LazyModule {
  val node = TLHelper.makeClientNode(TLMasterParameters.v1(
    name = "my-client",
    sourceId = IdRange(0, 4),
    requestFifo = true,
    visibility = Seq(AddressSet(0x10000, 0xffff))))

  lazy val module = new LazyModuleImp(this) {
    val (tl, edge) = node.out(0)

    // Rest of code here
  }
}

The name argument identifies the node in the Diplomacy graph. It is the only required argument for TLClientParameters.

The sourceId argument specifies the range of source identifiers that this client will use. Since we have set the range to [0, 4) here, this client will be able to send up to four requests in flight at a time. Each request will have a distinct value in its source field. The default value for this field is IdRange(0, 1), which means it would only be able to send a single request inflight.

The requestFifo argument is a boolean option which defaults to false. If it is set to true, the client will request that downstream managers that support it send responses in FIFO order (that is, in the same order the corresponding requests were sent).

The visibility argument specifies the address ranges that the client will access. By default it is set to include all addresses. In this example, we set it to contain a single address range AddressSet(0x10000, 0xffff), which means that the client will only be able to access addresses from 0x10000 to 0x1ffff. normally do not specify this, but it can help downstream crossbar generators optimize the hardware by not arbitrating the client to managers with address ranges that don’t overlap with its visibility.

Inside your lazy module implementation, you can call node.out to get a list of bundle/edge pairs. If you used the TLHelper, you only specified a single client edge, so this list will only have one pair.

The tl bundle is a Chisel hardware bundle that connects to the IO of this module. It contains two (in the case of TL-UL and TL-UH) or five (in the case of TL-C) decoupled bundles corresponding to the TileLink channels. This is what you should connect your hardware logic to in order to actually send/receive TileLink messages.

The edge object represents the edge of the Diplomacy graph. It contains some useful helper functions which will be documented in TileLink Edge Object Methods.

9.1.2. Manager Node

TileLink managers take requests from clients on the A channel and send responses back on the D channel. You can create a manager node using the TLHelper like so:

class MyManager(implicit p: Parameters) extends LazyModule {
  val device = new SimpleDevice("my-device", Seq("tutorial,my-device0"))
  val beatBytes = 8
  val node = TLHelper.makeManagerNode(beatBytes, TLSlaveParameters.v1(
    address = Seq(AddressSet(0x20000, 0xfff)),
    resources = device.reg,
    regionType = RegionType.UNCACHED,
    executable = true,
    supportsArithmetic = TransferSizes(1, beatBytes),
    supportsLogical = TransferSizes(1, beatBytes),
    supportsGet = TransferSizes(1, beatBytes),
    supportsPutFull = TransferSizes(1, beatBytes),
    supportsPutPartial = TransferSizes(1, beatBytes),
    supportsHint = TransferSizes(1, beatBytes),
    fifoId = Some(0)))

  lazy val module = new LazyModuleImp(this) {
    val (tl, edge) = node.in(0)
  }
}

The makeManagerNode method takes two arguments. The first is beatBytes, which is the physical width of the TileLink interface in bytes. The second is a TLManagerParameters object.

The only required argument for TLManagerParameters is the address, which is the set of address ranges that this manager will serve. This information is used to route requests from the clients. In this example, the manager will only take requests for addresses from 0x20000 to 0x20fff. The second argument in AddressSet is a mask, not a size. You should generally set it to be one less than a power of two. Otherwise, the addressing behavior may not be what you expect.

The second argument is resources, which is usually retrieved from a Device object. In this case, we use a SimpleDevice object. This argument is necessary if you want to add an entry to the DeviceTree in the BootROM so that it can be read by a Linux driver. The two arguments to SimpleDevice are the name and compatibility list for the device tree entry. For this manager, then, the device tree entry would look like

L12: my-device@20000 {
    compatible = "tutorial,my-device0";
    reg = <0x20000 0x1000>;
};

The next argument is regionType, which gives some information about the caching behavior of the manager. There are seven region types, listed below:

  1. CACHED - An intermediate agent may have cached a copy of the region for you.

  2. TRACKED - The region may have been cached by another master, but coherence is being provided.

  3. UNCACHED - The region has not been cached yet, but should be cached when possible.

  4. IDEMPOTENT - Gets return most recently put content, but content should not be cached.

  5. VOLATILE - Content may change without a put, but puts and gets have no side effects.

  6. PUT_EFFECTS - Puts produce side effects and so must not be combined/delayed.

  7. GET_EFFECTS - Gets produce side effects and so must not be issued speculatively.

Next is the executable argument, which determines if the CPU is allowed to fetch instructions from this manager. By default it is false, which is what most MMIO peripherals should set it to.

The next six arguments start with support and determine the different A channel message types that the manager can accept. The definitions of the message types are explained in TileLink Edge Object Methods. The TransferSizes case class specifies the range of logical sizes (in bytes) that the manager can accept for the particular message type. This is an inclusive range and all logical sizes must be powers of two. So in this case, the manager can accept requests with sizes of 1, 2, 4, or 8 bytes.

The final argument shown here is the fifoId setting, which determines which FIFO domain (if any) the manager is in. If this argument is set to None (the default), the manager will not guarantee any ordering of the responses. If the fifoId is set, it will share a FIFO domain with all other managers that specify the same fifoId. This means that client requests sent to that FIFO domain will see responses in the same order.

9.1.3. Register Node

While you can directly specify a manager node and write all of the logic to handle TileLink requests, it is usually much easier to use a register node. This type of node provides a regmap method that allows you to specify control/status registers and automatically generates the logic to handle the TileLink protocol. More information about how to use register nodes can be found in Register Router.

9.1.4. Identity Node

Unlike the previous node types, which had only inputs or only outputs, the identity node has both. As its name suggests, it simply connects the inputs to the outputs unchanged. This node is mainly used to combine multiple nodes into a single node with multiple edges. For instance, say we have two client lazy modules, each with their own client node.

class MyClient1(implicit p: Parameters) extends LazyModule {
  val node = TLHelper.makeClientNode("my-client1", IdRange(0, 1))

  lazy val module = new LazyModuleImp(this) {
    // ...
  }
}

class MyClient2(implicit p: Parameters) extends LazyModule {
  val node = TLHelper.makeClientNode("my-client2", IdRange(0, 1))

  lazy val module = new LazyModuleImp(this) {
    // ...
  }
}

Now we instantiate these two clients in another lazy module and expose their nodes as a single node.

class MyClientGroup(implicit p: Parameters) extends LazyModule {
  val client1 = LazyModule(new MyClient1)
  val client2 = LazyModule(new MyClient2)
  val node = TLIdentityNode()

  node := client1.node
  node := client2.node

  lazy val module = new LazyModuleImp(this) {
    // Nothing to do here
  }
}

We can also do the same for managers.

class MyManager1(beatBytes: Int)(implicit p: Parameters) extends LazyModule {
  val node = TLHelper.makeManagerNode(beatBytes, TLSlaveParameters.v1(
    address = Seq(AddressSet(0x0, 0xfff))))

  lazy val module = new LazyModuleImp(this) {
    // ...
  }
}

class MyManager2(beatBytes: Int)(implicit p: Parameters) extends LazyModule {
  val node = TLHelper.makeManagerNode(beatBytes, TLSlaveParameters.v1(
    address = Seq(AddressSet(0x1000, 0xfff))))

  lazy val module = new LazyModuleImp(this) {
    // ...
  }
}

class MyManagerGroup(beatBytes: Int)(implicit p: Parameters) extends LazyModule {
  val man1 = LazyModule(new MyManager1(beatBytes))
  val man2 = LazyModule(new MyManager2(beatBytes))
  val node = TLIdentityNode()

  man1.node := node
  man2.node := node

  lazy val module = new LazyModuleImp(this) {
    // Nothing to do here
  }
}

If we want to connect the client and manager groups together, we can now do this.

class MyClientManagerComplex(implicit p: Parameters) extends LazyModule {
  val client = LazyModule(new MyClientGroup)
  val manager = LazyModule(new MyManagerGroup(8))

  manager.node :=* client.node

  lazy val module = new LazyModuleImp(this) {
    // Nothing to do here
  }
}

The meaning of the :=* operator is explained in more detail in the Diplomacy Connectors section. In summary, it connects two nodes together using multiple edges. The edges in the identity node are assigned in order, so in this case client1.node will eventually connect to manager1.node and client2.node will connect to manager2.node.

The number of inputs to an identity node should match the number of outputs. A mismatch will cause an elaboration error.

9.1.5. Adapter Node

Like the identity node, the adapter node takes some number of inputs and produces the same number of outputs. However, unlike the identity node, the adapter node does not simply pass the connections through unchanged. It can change the logical and physical interfaces between input and output and rewrite messages going through. RocketChip provides a library of adapters, which are catalogued in Diplomatic Widgets.

You will rarely need to create an adapter node yourself, but the invocation is as follows.

val node = TLAdapterNode(
  clientFn = { cp =>
    // ..
  },
  managerFn = { mp =>
    // ..
  })

The clientFn is a function that takes the TLClientPortParameters of the input as an argument and returns the corresponding parameters for the output. The managerFn takes the TLManagerPortParameters of the output as an argument and returns the corresponding parameters for the input.

9.1.6. Nexus Node

The nexus node is similar to the adapter node in that it has a different output interface than input interface. But it can also have a different number of inputs than it does outputs. This node type is mainly used by the TLXbar widget, which provides a TileLink crossbar generator. You will also likely not need to define this node type manually, but its invocation is as follows.

val node = TLNexusNode(
  clientFn = { seq =>
    // ..
  },
  managerFn = { seq =>
    // ..
  })

This has similar arguments as the adapter node’s constructor, but instead of taking single parameters objects as arguments and returning single objects as results, the functions take and return sequences of parameters. And as you might expect, the size of the returned sequence need not be the same size as the input sequence.

Previous Next

© Copyright 2019, Berkeley Architecture Research. Revision bdeb496e.

Built with Sphinx using a theme provided by Read the Docs.
Read the Docs v: run-ci
Versions
latest
stable
1.8.0
1.7.1
1.7.0
1.6.2
1.6.1
1.6.0
1.5.0
1.4.0
1.3.0
1.2.0
1.1.0
1.0.0
run-ci
main
dev
conda
Downloads
pdf
html
epub
On Read the Docs
Project Home
Builds