Welcome to Chipyard’s documentation!¶
Chipyard is a framework for designing and evaluating full-system hardware using agile teams. It is composed of a collection of tools and libraries designed to provide an integration between open-source and commercial tools for the development of systems-on-chip.
Important
New to Chipyard? Jump to the Initial Repository Setup page for setup instructions.
Getting Help¶
If you have a question about Chipyard that isn’t answered by the existing documentation, feel free to ask for help on the Chipyard Google Group.
Table of Contents¶
- 1. Chipyard Basics
- 2. Simulation
- 3. Included RTL Generators
- 4. Development Tools
- 5. VLSI Flow
- 6. Customization
- 6.1. Heterogeneous SoCs
- 6.2. Integrating Custom Chisel Projects into the Generator Build System
- 6.3. Adding a custom core
- 6.4. RoCC vs MMIO
- 6.5. Adding a RoCC Accelerator
- 6.6. MMIO Peripherals
- 6.7. Dsptools Blocks
- 6.8. Keys, Traits, and Configs
- 6.9. Adding a DMA Device
- 6.10. Incorporating Verilog Blocks
- 6.11. Memory Hierarchy
- 6.12. Chipyard Boot Process
- 6.13. Adding a Firrtl Transform
- 6.14. IOBinders and HarnessBinders
- 7. Target Software
- 8. Advanced Concepts
- 9. TileLink and Diplomacy Reference
- 9.1. TileLink Node Types
- 9.2. Diplomacy Connectors
- 9.3. TileLink Edge Object Methods
- 9.4. Register Router
- 9.5. Diplomatic Widgets
- 9.5.1. TLBuffer
- 9.5.2. AXI4Buffer
- 9.5.3. AXI4UserYanker
- 9.5.4. AXI4Deinterleaver
- 9.5.5. TLFragmenter
- 9.5.6. AXI4Fragmenter
- 9.5.7. TLSourceShrinker
- 9.5.8. AXI4IdIndexer
- 9.5.9. TLWidthWidget
- 9.5.10. TLFIFOFixer
- 9.5.11. TLXbar and AXI4Xbar
- 9.5.12. TLToAXI4 and AXI4ToTL
- 9.5.13. TLROM
- 9.5.14. TLRAM and AXI4RAM
- 10. Prototyping Flow