2. Simulation
Chipyard supports two classes of simulation:
Software RTL simulation using commercial or open-source (Verilator) RTL simulators
FPGA-accelerated full-system simulation using FireSim
Software RTL simulators of Chipyard designs run at O(1 KHz), but compile quickly and provide full waveforms. Conversely, FPGA-accelerated simulators run at O(100 MHz), making them appropriate for booting an operating system and running a complete workload, but have multi-hour compile times and poorer debug visibility.
Click next to see how to run a simulation.
- 2.1. Software RTL Simulation
- 2.1.1. Verilator (Open-Source)
- 2.1.2. Synopsys VCS (License Required)
- 2.1.3. Choice of Simulator
- 2.1.4. Simulating The Default Example
- 2.1.5. Custom Benchmarks/Tests
- 2.1.6. Makefile Variables and Commands
- 2.1.7. Simulating A Custom Project
- 2.1.8. Fast Memory Loading
- 2.1.9. Generating Waveforms
- 2.1.10. Visualizing Chipyard SoCs
- 2.1.11. Additional Verilator Options
- 2.1.12. Speeding up your RTL Simulation by 2x!
- 2.2. FPGA-Accelerated Simulation