6. Customization

These guides will walk you through customization of your system-on-chip:

• Constructing heterogenous systems-on-chip using the existing Chipyard generators and configuration system.

• Constructing SoCs with a NoC (network-on-chip) based interconnect using Constellation

• How to include your custom Chisel sources in the Chipyard build system

• Adding custom core

• Adding custom RoCC accelerators to an existing Chipyard core (BOOM or Rocket)

• Adding custom MMIO widgets to the Chipyard memory system by Tilelink or AXI4, with custom Top-level IOs

• Adding custom Dsptools based blocks as MMIO widgets.

• Standard practices for using Keys, Traits, and Configs to parameterize your design

• Customizing the memory hierarchy

• Connect widgets which act as TileLink masters

• Adding custom blackboxed Verilog to a Chipyard design

We also provide information on:

• The boot process for Chipyard SoCs

• Examples of FIRRTL transforms used in Chipyard, and where they are specified

We recommend reading all these pages in order. Hit next to get started!

Customization:

• 6.1. Heterogeneous SoCs
  • 6.1.1. Creating a Rocket and BOOM System
  • 6.1.2. Adding Hwachas
  • 6.1.3. Assigning Accelerators to Specific Tiles with MultiRoCC
• 6.2. SoCs with NoC-based Interconnects
  • 6.2.1. Private Interconnects
  • 6.2.2. Shared Global Interconnect
• 6.3. Integrating Custom Chisel Projects into the Generator Build System
• 6.4. Adding a custom core
  • 6.4.1. Wrap Verilog Module with Blackbox (Optional)
  • 6.4.2. Create Parameter Case Classes
  • 6.4.3. Create Tile Class
  • 6.4.4. Connect TileLink Buses
  • 6.4.5. Create Implementation Class
  • 6.4.6. Connect Interrupt
  • 6.4.7. Create Config Fragments to Integrate the Core
• 6.5. RoCC vs MMIO
• 6.6. Adding a RoCC Accelerator
  • 6.6.1. Accessing Memory via L1 Cache
  • 6.6.2. Adding RoCC accelerator to Config
• 6.7. MMIO Peripherals
  • 6.7.1. Advanced Features of RegField Entries
  • 6.7.2. Connecting by TileLink
  • 6.7.3. Top-level Traits
  • 6.7.4. Constructing the DigitalTop and Config
  • 6.7.5. Testing
• 6.8. Dsptools Blocks
  • 6.8.1. Creating a DspBlock
  • 6.8.2. Connecting DspBlock by TileLink
  • 6.8.3. Top Level Traits
  • 6.8.4. Constructing the Top and Config
  • 6.8.5. FIR Testing
• 6.9. Keys, Traits, and Configs
  • 6.9.1. Keys
  • 6.9.2. Traits
  • 6.9.3. Config Fragments
  • 6.9.4. Chipyard Config Fragments
• 6.10. Adding a DMA Device
• 6.11. Incorporating Verilog Blocks
  • 6.11.1. Adding a Verilog Blackbox Resource File
  • 6.11.2. Defining a Chisel BlackBox
  • 6.11.3. Instantiating the BlackBox and Defining MMIO
  • 6.11.4. Defining a Chip with a BlackBox
  • 6.11.5. Software Testing
  • 6.11.6. Support for Verilog Within Chipyard Tool Flows
• 6.12. Memory Hierarchy
  • 6.12.1. The L1 Caches
  • 6.12.2. The System Bus
  • 6.12.3. The SiFive L2 Cache
  • 6.12.4. The Broadcast Hub
  • 6.12.5. The Outer Memory System
• 6.13. Chipyard Boot Process
  • 6.13.1. BootROM and RISC-V Frontend Server
  • 6.13.2. The Berkeley Boot Loader and RISC-V Linux
• 6.14. Adding a Firrtl Transform
  • 6.14.1. The Scala FIRRTL Compiler and the MLIR FIRRTL Compiler
  • 6.14.2. Where to add transforms
  • 6.14.3. Examples of transforms
• 6.15. IOBinders and HarnessBinders
  • 6.15.1. IOBinders
  • 6.15.2. HarnessBinders