Welcome to Chipyard’s documentation (version “main”)!
Chipyard is a framework for designing and evaluating full-system hardware using agile teams. It is composed of a collection of tools and libraries designed to provide an integration between open-source and commercial tools for the development of systems-on-chip. This work is supported by the NSF CCRI ENS Chipyard Award #201662.
Important
New to Chipyard? Jump to the Initial Repository Setup page for setup instructions.
Getting Help
Section titled “Getting Help”If you have a question about Chipyard that isn’t answered by the existing documentation, feel free to ask for help on the Chipyard Google Group.
Table of Contents
Section titled “Table of Contents”- Chipyard Basics
- Simulation
- Software RTL Simulation
- Verilator (Open-Source)
- Synopsys VCS (License Required)
- Choice of Simulator
- Simulating The Default Example
- Custom Benchmarks/Tests
- Makefile Variables and Commands
- Simulating A Custom Project
- Fast Memory Loading
- Generating Waveforms
- Visualizing Chipyard SoCs
- Additional Verilator Options
- Speeding up your RTL Simulation by 2x!
- FPGA-Accelerated Simulation
- Software RTL Simulation
- Included RTL Generators
- Development Tools
- VLSI Flow
- Customization
- Heterogeneous SoCs
- SoCs with NoC-based Interconnects
- Integrating Custom Chisel Projects into the Generator Build System
- Adding a custom core
- RoCC vs MMIO
- Adding a RoCC Accelerator
- MMIO Peripherals
- Dsptools Blocks
- Keys, Traits, and Configs
- Adding a DMA Device
- Incorporating Verilog Blocks
- Incorporating HLS
- Memory Hierarchy
- Chipyard Boot Process
- IOBinders and HarnessBinders
- Target Software
- Advanced Concepts
- TileLink and Diplomacy Reference
- Prototyping Flow