Running a Design on Genesys 2

Genesys 2 Instructions

The default Digilent Genesys 2 harness uses a TSI-over-UART adapter to bring up the FPGA and DDR for backing memory. A user can connect to the Genesys 2 target using the uart_tsi program that opens a UART TTY.

An example tweaks + Rocket config fragment can be found below:

// https://ucb.bar/chipyard/fpga/src/main/scala/genesys2/Configs.scala
class WithGenesys2Tweaks(freqMHz: Double = 50) extends Config(
  new WithGenesys2UARTTSI ++
  new WithGenesys2DDRTL ++
  new WithNoDesignKey ++
  new testchipip.tsi.WithUARTTSIClient ++
  new chipyard.harness.WithSerialTLTiedOff ++
  new chipyard.harness.WithHarnessBinderClockFreqMHz(freqMHz) ++
  new chipyard.config.WithUniformBusFrequencies(freqMHz) ++
  new chipyard.harness.WithAllClocksFromHarnessClockInstantiator ++
  new chipyard.clocking.WithPassthroughClockGenerator ++
  new chipyard.config.WithNoDebug ++ // no jtag
  new chipyard.config.WithNoUART ++ // use UART for the UART-TSI thing instad
  new chipyard.config.WithTLBackingMemory ++ // FPGA-shells converts the AXI to TL for us
  new freechips.rocketchip.subsystem.WithExtMemSize(BigInt(1024) << 20) ++ // 1gb on Genesys2
  new freechips.rocketchip.subsystem.WithoutTLMonitors)

class RocketGenesys2Config extends Config(
  new WithGenesys2Tweaks ++
  new chipyard.config.WithBroadcastManager ++ // no l2
  new chipyard.RocketConfig)

To build the design (Vivado should be added to the PATH), run:

cd fpga/
make SUB_PROJECT=genesys2 bitstream

To build the UART-based frontend server, run:

cd generators/testchipip/uart_tsi
make

After programming the bitstream and connecting the Genesys 2 UART to a host PC via the USB cable, the uart_tsi program can be run to interact with the target.

Running a program:

./uart_tsi +tty=/dev/ttyUSBX dhrystone.riscv

Probe an address on the target system:

./uart_tsi +tty=/dev/ttyUSBX +init_read=0x10000 none

Write an address before running a program:

./uart_tsi +tty=/dev/ttyUSBX +init_write=0x80000000:0xdeadbeef none

Self-check that binary loading proceeded correctly:

./uart_tsi +tty=/dev/ttyUSBX +selfcheck dhrystone.riscv