Welcome to Chipyard’s documentation (version “HEAD”)!
Chipyard is a framework for designing and evaluating full-system hardware using agile teams. It is composed of a collection of tools and libraries designed to provide an integration between open-source and commercial tools for the development of systems-on-chip. This work is supported by the NSF CCRI ENS Chipyard Award #201662.
Important
New to Chipyard? Jump to the Initial Repository Setup page for setup instructions.
Getting Help
If you have a question about Chipyard that isn’t answered by the existing documentation, feel free to ask for help on the Chipyard Google Group.
Table of Contents
- 1. Chipyard Basics
- 2. Simulation
- 2.1. Software RTL Simulation
- 2.1.1. Verilator (Open-Source)
- 2.1.2. Synopsys VCS (License Required)
- 2.1.3. Choice of Simulator
- 2.1.4. Simulating The Default Example
- 2.1.5. Custom Benchmarks/Tests
- 2.1.6. Makefile Variables and Commands
- 2.1.7. Simulating A Custom Project
- 2.1.8. Fast Memory Loading
- 2.1.9. Generating Waveforms
- 2.1.10. Visualizing Chipyard SoCs
- 2.1.11. Additional Verilator Options
- 2.1.12. Speeding up your RTL Simulation by 2x!
- 2.2. FPGA-Accelerated Simulation
- 2.1. Software RTL Simulation
- 3. Included RTL Generators
- 3.1. Rocket Chip
- 3.2. Rocket Core
- 3.3. Berkeley Out-of-Order Machine (BOOM)
- 3.4. Constellation
- 3.5. Gemmini
- 3.6. Saturn
- 3.7. IceNet
- 3.8. Test Chip IP
- 3.9. Rocket-Chip Generators
- 3.10. CVA6 Core
- 3.11. Ibex Core
- 3.12. VexiiRiscv Core
- 3.13. FFT Generator
- 3.14. NVDLA
- 3.15. Sodor Core
- 3.16. Shuttle RISC-V Core
- 3.17. Mempress
- 3.18. CompressAcc
- 3.19. Prefetchers
- 3.20. Ara
- 4. Development Tools
- 5. VLSI Flow
- 6. Customization
- 6.1. Heterogeneous SoCs
- 6.2. SoCs with NoC-based Interconnects
- 6.3. Integrating Custom Chisel Projects into the Generator Build System
- 6.4. Adding a custom core
- 6.5. RoCC vs MMIO
- 6.6. Adding a RoCC Accelerator
- 6.7. MMIO Peripherals
- 6.8. Dsptools Blocks
- 6.9. Keys, Traits, and Configs
- 6.10. Adding a DMA Device
- 6.11. Incorporating Verilog Blocks
- 6.11.1. Adding a Verilog Blackbox Resource File
- 6.11.2. Defining a Chisel BlackBox
- 6.11.3. Instantiating the BlackBox and Defining MMIO
- 6.11.4. Defining a Chip with a BlackBox
- 6.11.5. Software Testing
- 6.11.6. Support for Verilog Within Chipyard Tool Flows
- 6.11.7. Differences between
HasBlackBoxPath
andHasBlackBoxResource
- 6.12. Incorporating HLS
- 6.13. Memory Hierarchy
- 6.14. Chipyard Boot Process
- 6.15. IOBinders and HarnessBinders
- 7. Target Software
- 8. Advanced Concepts
- 9. TileLink and Diplomacy Reference
- 9.1. TileLink Node Types
- 9.2. Diplomacy Connectors
- 9.3. TileLink Edge Object Methods
- 9.4. Register Node
- 9.5. Diplomatic Widgets
- 9.5.1. TLBuffer
- 9.5.2. AXI4Buffer
- 9.5.3. AXI4UserYanker
- 9.5.4. AXI4Deinterleaver
- 9.5.5. TLFragmenter
- 9.5.6. AXI4Fragmenter
- 9.5.7. TLSourceShrinker
- 9.5.8. AXI4IdIndexer
- 9.5.9. TLWidthWidget
- 9.5.10. TLFIFOFixer
- 9.5.11. TLXbar and AXI4Xbar
- 9.5.12. TLToAXI4 and AXI4ToTL
- 9.5.13. TLROM
- 9.5.14. TLRAM and AXI4RAM
- 10. Prototyping Flow