6.12. Incorporating HLS

High Level Synthesis (HLS) is a method for iterating quickly on different hardware algorithms that automatically generates an RTL circuit to match a specification in a high level language like C.

Here, we will integrate an HLS-generated accelerator that computes the Great Common Denominator (GCD) of two integers. This tutorial builds on the sections MMIO Peripherals and Incorporating Verilog Blocks.

6.12.1. Adding an HLS project

In this tutorial, we use Vitis HLS. The user guide for this tool can be found at https://docs.amd.com/r/en-US/ug1399-vitis-hls.

Our project consists of 3 HLS files: * C program of the GCD algorithm: generators/chipyard/src/main/resources/hls/HLSAccel.cpp * TCL script to run Vitis HLS: generators/chipyard/src/main/resources/hls/run_hls.tcl * Makefile to run HLS and move verilog files: generators/chipyard/src/main/resources/hls/Makefile

This example implements an iterative GCD algorithm, which is manually connected to a TileLink register node in the HLSGCDAccel class in generators/chipyard/src/main/scala/example/GCD.scala. HLS also supports adding AXI nodes to accelerators using compiler directives and the HLS stream library. See the Vitis HLS user guide for AXI implementation information.

The HLS code is synthesized for a particular FPGA target, in this case, an AMD Alveo U200. The target FPGA part is specified in run_hls.tcl using the set_part command. The clock period, used for design optimization purposes, is also set in run_hls.tcl using the create_clock command.

To generate the verilog files, as well as synthesis reports, run:

vitis_hls run_hls.tcl

The files can be found in a generated folder named proj_<your_project_name>, in our case, proj_gcd_example.

In our case, we include a Makefile to run HLS and to move files to their intended locations. To generate the verilog files using the Makefile, run:

make

To delete the generated files, run:

make clean

6.12.2. Creating the Verilog black box

Note

This section discusses automatically running HLS within a Verilog black box. Please consult Incorporating Verilog Blocks for background information on writing a Verilog black box.

We use Scala to run make, which runs HLS and copies the files into generators/chipyard/src/main/resources/vsrc. Then, we add the path to each file. This code will execute during Chisel elaboration, conveniently handling file generation for the user.

class HLSGCDAccelBlackBox(val w: Int) extends BlackBox with HasBlackBoxPath {
  val io = IO(new HLSGCDAccelIO(w))

  val chipyardDir = System.getProperty("user.dir")
  val hlsDir = s"$chipyardDir/generators/chipyard"
  
  // Run HLS command
  val make = s"make -C ${hlsDir}/src/main/resources/hls default"
  require (make.! == 0, "Failed to run HLS")

  // Add each vlog file
  addPath(s"$hlsDir/src/main/resources/vsrc/HLSGCDAccelBlackBox.v")
  addPath(s"$hlsDir/src/main/resources/vsrc/HLSGCDAccelBlackBox_flow_control_loop_pipe.v")
}

6.12.3. Running the example

To test if the accelerator works, use the test program in tests/gcd.c. Compile the program with make. Then, run:

cd sims/vcs
make run-binary CONFIG=HLSAcceleratorRocketConfig BINARY=../../tests/gcd.riscv