3. Included RTL Generators
A Generator can be thought of as a generalized RTL design, written using a mix of meta-programming and standard RTL. This type of meta-programming is enabled by the Chisel hardware description language (see Chisel). A standard RTL design is essentially just a single instance of a design coming from a generator. However, by using meta-programming and parameter systems, generators can allow for integration of complex hardware designs in automated ways. The following pages introduce the generators integrated with the Chipyard framework.
Chipyard bundles the source code for the generators, under the generators/
directory.
It builds them from source each time (although the build system will cache results if they have not changed),
so changes to the generators themselves will automatically be used when building with Chipyard and propagate to software simulation, FPGA-accelerated simulation, and VLSI flows.
- 3.1. Rocket Chip
- 3.2. Rocket Core
- 3.3. Berkeley Out-of-Order Machine (BOOM)
- 3.4. Constellation
- 3.5. Gemmini
- 3.6. Saturn
- 3.7. IceNet
- 3.8. Test Chip IP
- 3.9. Rocket-Chip Generators
- 3.10. CVA6 Core
- 3.11. Ibex Core
- 3.12. VexiiRiscv Core
- 3.13. FFT Generator
- 3.14. NVDLA
- 3.15. Sodor Core
- 3.16. Shuttle RISC-V Core
- 3.17. Mempress
- 3.18. CompressAcc
- 3.19. Prefetchers
- 3.20. Ara