3.8. Test Chip IP

Chipyard includes a Test Chip IP library which provides various hardware widgets that may be useful when designing SoCs. This includes a SimTSI, Block Device Controller, TileLink SERDES, TileLink Switcher, TileLink Ring Network, and UART Adapter.

3.8.1. SimTSI

The SimTSI and TSIToTileLink are used by tethered test chips to communicate with the host processor. An instance of RISC-V frontend server running on the host CPU can send commands to the TSIToTileLink to read and write data from the memory system. The frontend server uses this functionality to load the test program into memory and to poll for completion of the program. More information on this can be found in Chipyard Boot Process.

3.8.2. Block Device Controller

The block device controller provides a generic interface for secondary storage. This device is primarily used in FireSim to interface with a block device software simulation model. The default Linux configuration in firesim-software

To add a block device to your design, add the WithBlockDevice config fragment to your configuration.

3.8.6. UART Adapter

The UART Adapter is a device that lives in the TestHarness and connects to the UART port of the DUT to simulate communication over UART (ex. printing out to UART during Linux boot). In addition to working with stdin/stdout of the host, it is able to output a UART log to a particular file using +uartlog=<NAME_OF_FILE> during simulation.

By default, this UART Adapter is added to all systems within Chipyard by adding the WithUART and WithUARTAdapter configs.

3.8.7. SPI Flash Model

The SPI flash model is a device that models a simple SPI flash device. It currently only supports single read, quad read, single write, and quad write instructions. The memory is backed by a file which is provided using +spiflash#=<NAME_OF_FILE>, where # is the SPI flash ID (usually 0).

3.8.8. Chip ID Pin

The chip ID pin sets the chip ID for the chip it is added to. This is most useful in multi-chip configs. The pin value is driven by the chip ID value set in the harness binder and the chip ID value can be read through MMIO at the address 0x2000 by default.

The pin can be added to a system with the testchipip.soc.WithChipIdPin config. The pin width and MMIO address are parameterizable and can be set by passing ChipIdPinParams as an argument to the config. The width can additionally be set using the testchipip.soc.WithChipIdPinWidth config.